Interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects

ABSTRACT

An interconnect includes a member that is integral and lacks a discernable boundary with a bit line, as well as metal nitride and metal silicide between the member and an active-device region of a semiconductor substrate. The interconnect may extend adjacent to and be insulated from a stacked capacitor structure to facilitate electrical communication between the active-device region and the bit line. Methods for fabricating such an interconnect are disclosed, as methods for fabricating semiconductor device structures that include one or more such interconnects.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/931,181,filed Aug. 30, 2004, which will issue as U.S. Pat. No. 7,057,285, onJun. 6, 2006, which is a continuation of application Ser. No.10/180,846, filed Jun. 26, 2002, now U.S. Pat. No. 6,787,428, issuedSep. 7, 2004, which is a continuation of application Ser. No.09/651,384, filed Aug. 29, 2000, now U.S. Pat. No. 6,465,319, issuedOct. 15, 2002, which is a continuation of application Ser. No.09/102,331, filed Jun. 22, 1998, now U.S. Pat. No. 6,165,863, issuedDec. 26, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to stacked capacitor structures ofsemiconductor devices. In particular, the present invention relates tosemiconductor device structures which include aluminum plugs disposedbetween the active device regions and bit lines thereof. Morespecifically, the present invention relates to semiconductor devicestructures which include an aluminum-filled trench that electricallyconnects a bit line to an active device region positioned betweenadjacent stacked capacitor structures.

2. Background of Related Art

Stacked capacitors are employed in many state of the art semiconductordevices to maintain high storage capacitance despite the ever-increasingdensities of such semiconductor devices. Stacked capacitors typicallymake an electrical connection with a diffusion region, or active deviceregion, of a semiconductor substrate, such as silicon, polysilicon,gallium arsenide, or indium phosphide. Some conventional processes forfabricating stacked capacitors on semiconductor device structuresfacilitate increased densities by employing electrically conductivelayers (e.g., polysilicon layers) that are somewhat convoluted or havelarge surface areas, and which project outwardly relative to andelectrically contact their associated active device regions. Theremainders of the capacitor structures are then fabricated on theelectrically conductive layers.

Many stacked capacitor structures include electrically conductivecontacts between the active device regions and the bit lines thereof.Typically, such electrically conductive contacts are fabricated frompolysilicon, which withstands the high temperature processes (e.g.,thermal oxidation processes or thermal anneal processes) that areusually performed subsequent to the fabrication of contacts onsemiconductor device structures. Such contacts, however, may create asomewhat undesirable amount of contact resistance during operation ofthe semiconductor device.

Metals have also been employed as the contact material between theactive device region and bit lines of semiconductor devices and throughthe stacked capacitor structures thereof. Again, due to the high processtemperatures that are employed following the fabrication of thecontacts, metals that will withstand high process temperatures aretypically employed in the contacts. Metals that will withstand such highprocess temperatures are commonly referred to as “refractory metals” andinclude titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).While these metals and their silicides have low resistivities relativeto other metals, their resistivities (ρ_(Ti)=43-47 μΩ-cm, ρ_(W)=5.3μΩ-cm, ρ_(Mo)=5 μΩ-cm, and ρ_(Ta)=13−16 μΩ-cm) may be somewhatundesirable during the operation of state of the art very large scaleintegration (VLSI) and ultra large scale integration (ULSI)semiconductor devices. As metals of higher resistivity are employed insuch semiconductor devices, the power requirements and operatingtemperature of such semiconductor devices increase undesirably.

Conventionally, aluminum (Al) has been widely employed as anelectrically conductive material in semiconductor devices, as it has lowresistivity (ρ_(Al)=2.7 μΩ-cm) and is compatible with both silicon (Si)and silicon dioxide (SiO₂). Aluminum is not, however, typically employedin self-aligned processes due to its inability to withstand hightemperature processing, such as the rapid thermal anneal processes thatmay be employed in fabricating self-aligned silicide layers.

What is needed is a process for fabricating a stacked capacitorstructure on a semiconductor device structure which increases the speedof the semiconductor device and reduces the interconnect resistance andpower consumption thereof and a stacked capacitor structure andsemiconductor device structure fabricated by such a process.

SUMMARY OF THE INVENTION

The present invention includes a stacked capacitor structure and methodsof fabricating the stacked capacitor structure which address theforegoing needs.

The stacked capacitor structure of the present invention includes atrench disposed over an active device region of a semiconductor devicestructure. The trench extends downward through the stacked capacitorstructure to the active device region of the semiconductor substrate(e.g., silicon, gallium arsenide, indium phosphide), exposing samethrough the stacked capacitor structure. A layer of self-aligned metalsilicide, or “salicide,” is disposed within the trench, adjacent theactive device region and preferably defining a buried metal diffusion(BMD) layer with the active device region. An aluminum interconnect, or“contact,” is disposed within the trench in contact with the metalsilicide and substantially filling the trench. The aluminum interconnectpreferably provides an electrical link between the active device regionand a bit line that extends above the stacked capacitor structure andelectrically contacts the interconnect.

A method of fabricating a stacked capacitor structure is also within thescope of the present invention. The method includes fabricating astacked capacitor structure over a semiconductor device structure anddefining a trench through the stacked capacitor structure and over anactive device region of the semiconductor device structure. Processesfor fabricating stacked capacitor structures and defining trenchestherethrough to an underlying active device region, which may beemployed in the method of the present invention, are disclosed in U.S.Pat. No. 5,498,562 (“the '562 patent”), which issued to Dennison et al.on Mar. 12, 1996, the disclosure of which is hereby incorporated byreference in its entirety.

A layer of a metal that will form a salicide with the silicon exposedthrough the trench, such as titanium or tungsten, is then deposited overthe semiconductor device structure. Known processes, such as rapidthermal anneal (RTA) or silicide deposition processes, may then beemployed to form the salicide layer, such as titanium silicide(TiSi_(x), predominantly TiSi₂) or tungsten silicide (WSi_(x),predominantly WSi₂), which is typically referred to as a “selective”contact, over the active device region of the semiconductor devicestructure. The formation of suicides such as TiSi₂ and WSi₂ is said tobe self-aligned since the silicide forms only over exposed semiconductorsubstrate (e.g., silicon and polysilicon) regions of a semiconductordevice structure. Everywhere else, the metal film overlies aninsulative, substantially non-reactive oxide layer, and may subsequentlybe removed. Preferably, the metal silicide diffuses into the silicon anddefines a BMD layer. A metal nitride layer may also be fabricated overthe selective contact by known techniques. Such metal nitride layers aretypically referred to as “barrier” layers, as they prevent the diffusionof silicon and silicide into any metal layer or structure that issubsequently fabricated adjacent thereto.

An interconnect is fabricated in the trench by depositing aluminum overthe semiconductor device structure in a manner that substantially fillsthe trench. Known processes, such as physical vapor deposition (PVD) andchemical vapor deposition (CVD) techniques, may be employed to depositaluminum over the semiconductor device structure. The aluminum thatcovers other areas of the semiconductor device structure may then beremoved by known processes, such as by known planarization (e.g., bychemical-mechanical polishing (CMP) techniques) or etching techniques,which do not remove aluminum from the trench. Additional layers andstructures may then be fabricated or defined above the stackedcapacitor, including, without limitation, bit lines that are inelectrical contact with one or more corresponding aluminuminterconnects.

Alternatively, portions of the aluminum layer that overlie thesemiconductor device structure may be selectively removed therefrom byknown techniques, such as masking and etching processes, in order todefine bit lines that are integral with the aluminum interconnects andextend over an active surface of the semiconductor device structure.Such aluminum bit lines may be desirable since they may further reducecontact resistance and are compatible with the adjacent silicon dioxideof the semiconductor device structure.

The advantages of the present invention will become apparent to those ofskill in the art through a consideration of the ensuing description, theaccompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a cross-sectional schematic representation of a semiconductordevice structure including an aluminum interconnect extending from anactive device region of the semiconductor substrate and through astacked capacitor structure to a bit line; and

FIGS. 2-8 are cross-sectional schematic representations which illustratea process of fabricating the semiconductor device structure of FIG. 1 inaccordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIG. 1, a semiconductor device structure 10 accordingto the present invention is shown. Semiconductor device structure 10includes a semiconductor substrate 12, such as silicon, galliumarsenide, or indium phosphide, a field oxide layer 14 disposed overvarious regions of semiconductor substrate 12, active device regions 16in semiconductor substrate 12, word lines 18 extending oversemiconductor substrate 12 and field oxide layer 14, and a stackedcapacitor structure 20 disposed over word lines 18 and active deviceregions 16.

A trench 22 extends through stacked capacitor structure 20, exposing asource/drain 24, or p-n region, of active device region 16 to an activesurface 11 of semiconductor device structure 10. A metal silicideselective contact 38 may be disposed over source/drain 24, andpreferably defines a buried metal diffusion layer 39 in thesemiconductor substrate 12 of source/drain 24. Selective contact 38preferably comprises titanium silicide. A metal nitride layer 40,preferably titanium nitride (TiN), may be disposed over selectivecontact 38. The remainder of trench 22 is filled with aluminum, whichdefines an aluminum interconnect 34, or contact or plug.

Aluminum interconnect 34 is in electrical communication with a bit line36 that extends over semiconductor device structure 10 above the stackedcapacitor structures 20 thereof. Bit line 36 may be fabricated from anelectrically conductive material, including, without limitation, metalssuch as aluminum, tungsten and titanium, electrically conductivepolymers, and doped polysilicon. If bit line 36 is fabricated fromaluminum, bit line 36 and aluminum interconnect 34 are preferablyintegral.

Referring now to FIGS. 2-8, a method of fabricating a semiconductordevice structure 10 in accordance with the present invention isillustrated. FIG. 2 illustrates a semiconductor device structure 10 withactive device regions 16, word lines 18, and a stacked capacitorstructure 20 disposed thereon. Each of these features may be fabricatedas known in the art, such as by the process disclosed in the '562patent.

Turning now to FIG. 3, a trench 22 is defined through stacked capacitorstructure 20 by known processes, such as the mask and anisotropic etchprocesses that are disclosed in the '562 patent. Any electricallyconductive features of the stacked capacitor structure 20, such as theelectrically conductive (typically polysilicon) layer 21 thereof, thatare exposed to trench 22 may be oxidized by known processes to insulatethese electrically conductive features from the subsequently fabricatedaluminum interconnect 34 (see FIG. 1), as disclosed in the '562 patent.Preferably, in order to prevent oxidation of source/drain 24 as anyexposed electrically conductive features of stacked capacitor structure20 are insulated, such insulation is performed before trench 22 has beencompletely defined and, therefore, prior to the exposure of source/drain24 through trench 22.

With reference to FIG. 4, a selective contact 38 of a metal silicide maythen be fabricated over source/drain 24. Metal silicides that may beemployed as selective contact 38 include, without limitation, titaniumsilicide (TiSi_(x), predominantly TiSi₂), tungsten silicide (WSi_(x),predominantly WSi₂), molybdenum silicide (MoSi_(x), predominantlyMoSi₂), and platinum silicide (PtSi_(x), predominantly PtSi₂). Knownprocesses may be employed to form selective contact 38. An exemplaryprocess for fabricating selective contact 38 includes the deposition ofa metal or metal nitride over semiconductor device structure 10, a rapidthermal anneal of the metal or metal nitride to the exposed regions ofsemiconductor substrate 12 to form the salicide selective contact 38,and removal of the non-reacted metal or metal nitride from the activesurface 11 of the semiconductor device structure 10.

Alternatively, selective contact 38 may be selectively deposited ontosource/drain 24 by chemical vapor deposition (CVD) of a metallicprecursor and a silicon-containing compound. For example, when titaniumsilicide selective contacts are desired, a titanium tetrahalide, such astitanium tetrachloride (TiCl₄), is reacted with either silane (SiH₄) ordichlorosilane (DCS, SiH₂Cl₂) as follows:TiCl₄+SiH₄→TiSi₂↓TiCl₄+SiH₂Cl₂→TiSi₂↓

In order to optimize the selectivity of these titanium silicidedeposition reactions for the semiconductor substrate 12, which isexposed through trench 22, a deposition temperature in the range ofabout 650° C. to about 750° C. is preferable. Since minimal amounts ofthe semiconductor substrate 12 are consumed by these reactions, thedeposition reaction is allowed to continue until a selective contact 38of the desired thickness is formed.

Other exemplary metal silicide deposition processes that may be employedin the present invention to fabricate selective contact 38 include thereaction of a titanium halide and/or a gaseous titanium organometallicprecursor with a silicon-containing compound of the formulaSi_(n)H_(2n+2), as disclosed in U.S. Pat. No. 5,240,739, issued to TrungDoan et al. on Aug. 31, 1993; U.S. Pat. No. 5,278,100, issued to TrungDoan et al. on Jan. 11, 1994; and U.S. Pat. No. 5,376,405, issued toTrung Doan et al. on Dec. 27, 1994, the disclosures of each of which arehereby incorporated by reference in their entirety. Titanium halidesthat may be employed in the deposition of selective contact 38 oversource/drain 24 include, without limitation, TiCl₄, titaniumtetraboride, titanium tetrafluoride, titanium tetraiodide, andsubhalides. Titanium organometallic precursors which may be used tofabricate selective contact 38 include, but are not limited to,compounds of the formula Ti(NR₂)₄, where the titanium atom is bonded tothe nitrogen atom and R comprises hydrogen or a carbon-containingradical. Exemplary compounds include tetradimethylamido titanium (TDMATor Ti(N(CH₃)₂)₄ and Ti(N(C₂H₅)₂)₄).

The following are exemplary chemical reactions for depositing metalsilicide on source/drain 24:nTiCl₄+Si_(n)H_(2n+2) →nTiSi+4nHCl+H₂+by-products;nTiCl₄+2Si_(n)H_(2n+2) →nTiSi+4nHCl+2H₂+by-products;TiCl₄+Si_(n)H_(2n+2)→Ti₅Si₃+HCl+H₂+by-products;TDMAT+Si₂H₆→TiSi₂+organic by-products;TDMAT+Si_(n)H_(2n+2)→(n/2)TiSi₂+organic by-products; andTi(NR₂)₄+SiH₄→TiSi_(x)+TiSi_(y)N_(1−y)+organic by-products,where x is predominantly equal to two, y is zero or one and n is aninteger equal to zero or more. The reaction between TiCl₄ and Si₂H₆ maybe employed to deposit selective contact 38 over source/drain 24 at atemperature as low as about 400° C. The reaction of TiCl₄ and Si₃H₈deposits a titanium silicide selective contact 38 on a semiconductorsubstrate 12 at a temperature of about 300° C. or higher.

Preferably, selective contact 38 and semiconductor substrate 12 diffuseinto each other to define a buried metal diffusion layer 39.

Although silicide deposition in accordance with the foregoing processesis selective for semiconductor substrate 12, residual metal silicide maybe deposited above stacked capacitor structure 20. Thus, cleaning ofsemiconductor device structure 10 may be desirable in order to removeany residual metal silicide from above stacked capacitor structure 20.Cleaning agents such as chlorine (Cl₂), hydrochloric acid (HCl) andhydrofluoric acid (HF) may be employed in known cleaning techniques(e.g., thermal gas, plasma assisted, and remote plasma activatedcleaning) to clean any residual metal silicides from field oxide layer14.

Referring now to FIG. 5, upon depositing a selective contact 38 of thedesired thickness, a metal nitride layer 40, which is also referred toas a barrier layer, may be deposited over selective contact 38. Ametallic precursor and another reactant, which are collectively referredto as second reactants, may be reacted to deposit metal nitride layer 40over semiconductor device structure 10. The metallic precursor, which ispreferably TiCl₄ when selective contact 38 is comprised of titaniumsilicide, is reacted with ammonia (NH₃) to initiate the followingchemical reaction, which deposits a metal nitride layer 40 of titaniumnitride over the surface of semiconductor device structure 10:TiCl₄+NH₃→TiN↓,including above the stacked capacitor structures 20 and selectivecontacts 38 of the semiconductor device structure 10 (i.e., a “blanket”deposition occurs). The duration of the foregoing reaction is dependentupon the desired thickness of metal nitride layer 40. This reaction mayalso be carried out in the presence of nitrogen gas (N₂), as discussedin U.S. Pat. No. 5,416,045 (“the '045 patent”), issued to Ralph E.Kauffman et al. on May 16, 1995, the disclosure of which is herebyincorporated by reference in its entirety. As explained in the '045patent, nitrogen gas facilitates the deposition of titanium nitride attemperatures of about 500° C. or lower. Hydrogen gas (H₂) may also beintroduced into the reaction chamber to facilitate the formation ofhydrochloric acid from chlorine.

Other chemical reactions are also useful for depositing metal nitridelayer 40. U.S. Pat. No. 5,399,379 (“the '379 patent”), issued to GurtejS. Sandhu on Mar. 21, 1995, the disclosure of which is herebyincorporated by reference in its entirety, describes such a reaction,whereby one or more organometallic compounds of the formula Ti(NR₂)₄,which is also referred to as a tetrakis-dialkylamido-titanium, arereacted with a halide gas (e.g., F₂, Cl₂, Br₂) to form a titaniumnitride film on a semiconductor device. In each Ti(NR₂)₄ molecule, thetitanium atom is single-bonded to four nitrogen atoms, each of which arealso single-bonded to two carbon-containing radical (R) groups, whichinclude hydrogen atoms or alkyl groups.

Another exemplary titanium nitride deposition reaction is disclosed inU.S. Pat. No. 5,254,499 (“the '499 patent”), issued to Gurtej S. Sandhuet al. on Oct. 19, 1993, the disclosure of which is hereby incorporatedby reference in its entirety. According to the '499 patent, a titaniumnitride layer may also be deposited by reacting one or more compounds ofthe general formula Ti(NR₂)₄, where the titanium atom is bonded to anitrogen atom, which is in turn bonded to two hydrogen atoms or acarbon-containing radical (R), with ammonia (NH₃). The following UnitedStates Patents disclose various other methods for depositing titaniumnitride films, wherein the second reactants are Ti(NR₂)₄ and ammonia:U.S. Pat. No. 5,192,589, issued to Gurtej S. Sandhu on Mar. 9, 1993;U.S. Pat. No. 5,139,825, issued to Roy G. Gordon et al. on Aug. 18,1992; and U.S. Pat. No. 5,089,438, issued to Avishay Katz on Feb. 18,1992, the disclosures of each of which are hereby incorporated byreference in their entirety.

U.S. Pat. No. 5,246,881, issued to Gurtej S. Sandhu et al. on Sep. 21,1993, the disclosure of which is hereby incorporated by reference in itsentirety, discloses another method for depositing a titanium nitridefilm, wherein the second reactants are one or more compounds of theformula Ti(NR₂)₄, where the titanium atom is bonded to the nitrogen atomwhich is, in turn, bonded to two hydrogen atoms or a carbon-containingradical (R), and an activated species which attacks the R-nitrogen bondsof the Ti(NR₂)₄, and which will convert the activated species to avolatile compound. The activated species include halogens, ammonia, andhydrogen, and are radiofrequency (RF) activated remote from theTi(NR₂)₄.

Another titanium nitride deposition reaction that is useful in themethod of the present invention is disclosed in U.S. Pat. No. 5,227,334,issued to Gurtej S. Sandhu on Jul. 13, 1993, which is herebyincorporated by reference in its entirety. The second reactants of thatprocess include a titanium-containing compound, such as Ti(NR₂)₄, andnitrogen trifluoride (NF₃).

Alternatively, metal nitride layer 40 may comprise a mixed phase layer,such as the TiN/TiSi_(x) layer deposited by the method disclosed in U.S.Pat. No. 5,252,518 (“the '518 patent”), issued to Gurtej S. Sandhu etal. on Oct. 12, 1993, the disclosure of which is hereby incorporated byreference in its entirety. The process of the '518 patent includesreacting Ti(NR₂)₄, where the titanium atom is bonded to the nitrogenatom which is, in turn, bonded to two hydrogen atoms or acarbon-containing radical (R), with an organic silane reactive gas, suchas tris(dimethylamino) silane (SIN).

FIG. 6 illustrates the selective removal of metal nitride layer 40 fromthe active surface 11 of semiconductor device structure 10. Knownpatterning processes, such as mask and etch techniques, may be employedto selectively remove metal nitride layer 40 from various regions ofsemiconductor device structure 10 (e.g., from above the stackedcapacitor structures 20 thereof), while metal nitride layer 40 remainsover selective contact 38. Alternatively, a layer 42 (see FIG. 7) ofaluminum may be disposed over metal nitride layer 40 prior to suchpatterning.

With reference to FIG. 7, a layer 42 of aluminum may be disposed oversemiconductor device structure 10 and within trench 22 by knownprocesses, such as PVD (e.g., sputtering, evaporation, or other PVDprocesses) or CVD. Aluminum layer 42 may be patterned by knowntechniques, such as masking and etching, to define bit lines 36 (seeFIG. 1) therefrom and integral therewith. Alternatively, the layer 42 ofaluminum overlying semiconductor device structure 10 may besubstantially completely removed from above the stacked capacitorstructures 20 thereof by known techniques, such as etch processes orplanarization processes (e.g., chemical/mechanical planarization (CMP))that will leave aluminum interconnect 34 substantially intact.

Referring to FIG. 8, if aluminum layer 42 is removed from active surface11, a bit line 36 comprised of an electrically conductive material, suchas a metal (e.g., tungsten, titanium, aluminum), an electricallyconductive polymer, or polysilicon, may be fabricated above stackedcapacitor structure 20 and in electrical contact with aluminuminterconnect 34. Known metal layer fabrication processes, such as PVD orCVD processes, may be employed to deposit a layer of metal from whichbit line 36 is to be defined by known patterning techniques, such asmask and etch processes.

Additional structures and layers may then be fabricated over the activesurface 11 of semiconductor device structure 10 by known processes.

The semiconductor device structure 10 (see FIG. 1) of the presentinvention may have increased speed and lower power consumption than manystate of the art semiconductor devices due to the use of aluminum, whichhas a low resistivity, in interconnects 34 and due to the salicideselective contact 38 and the buried metal diffusion layer 39, each ofwhich may reduce contact resistance.

In addition, the aluminum interconnects 34 of semiconductor devicestructure 10 of the present invention may also facilitate furtherincreases in the density of semiconductor device structures due to thelow resistivity of aluminum and, thus, the potentially thinnerinterconnects 34 that may be fabricated through the stacked capacitorstructures 20 of such semiconductor devices.

Although the foregoing description contains many specifics, these shouldnot be construed as limiting the scope of the present invention, butmerely as providing illustrations of some of the presently preferredembodiments. Similarly, other embodiments of the invention may bedevised which do not depart from the spirit or scope of the presentinvention. Features from different embodiments may be employed incombination. The scope of the invention is, therefore, indicated andlimited only by the appended claims and their legal equivalents, ratherthan by the foregoing description. All additions, deletions andmodifications to the invention as disclosed herein which fall within themeaning and scope of the claims are to be embraced thereby.

1. An interconnect for connecting an active-device region of asemiconductor substrate to a bit line extending above a semiconductordevice structure, comprising: metal silicide in contact with theactive-device region; a member in communication with the bit line, themember and the bit line comprising a unitary structure with nodiscernable boundary therebetween; and metal nitride substantiallyconfined between the metal silicide and the member.
 2. The interconnectof claim 1, wherein the metal nitride comprises titanium nitride.
 3. Theinterconnect of claim 1, wherein the metal nitride and the membercomprise a buried metal diffusion structure.
 4. The interconnect ofclaim 1, wherein the metal silicide comprises at least one of titaniumsilicide and tungsten silicide.
 5. The interconnect of claim 1, whereinthe member has a resistivity of less than about 5 μΩ-cm.
 6. Theinterconnect of claim 1, wherein the member comprises aluminum.
 7. Aninterconnect for connecting an active-device region of a semiconductorsubstrate to a bit line extending above a semiconductor devicestructure, comprising: a member extending from the bit line, the memberand the bit line comprising a unitary structure with no discernableboundary therebetween; a metal silicide adjacent to the active-deviceregion; and metal nitride positioned between the metal silicide and themember, an entirety of the metal nitride being superimposed relative tothe metal silicide.
 8. The interconnect of claim 7, wherein the metalsilicide contacts the active-device region.
 9. The interconnect of claim7, wherein the metal silicide contacts the member.
 10. The interconnectof claim 7, wherein the metal nitride comprises titanium nitride. 11.The interconnect of claim 7, wherein adjacent portion of the metalsilicide and the member comprise a buried metal diffusion structure. 12.The interconnect of claim 7, wherein the metal silicide comprises atleast one of titanium silicide and tungsten silicide.
 13. Theinterconnect of claim 7, wherein the member has a resistivity of lessthan about 5 μΩ-cm.
 14. The interconnect of claim 7, wherein the membercomprises aluminum.
 15. A method for fabricating a semiconductor devicestructure, comprising: forming at least one trench through at least onestacked capacitor structure to expose at least one active device region;forming a buried metal diffusion layer within the trench; forming metalnitride adjacent to the buried metal diffusion layer; concurrentlyintroducing conductive material over the at least one stacked capacitorstructure and within the at least one trench, the metal nitridesubstantially confined between the buried metal diffusion layer and theconductive material; and forming at least one bit line from conductivematerial located over at least the at least one stacked capacitorstructure, with no discernable boundary between the at least one bitline and at least one member formed by conductive material within the atleast one trench.
 16. The method of claim 15, further comprising:electrically isolating the at least one trench from the at least onestacked capacitor structure.
 17. The method of claim 15, wherein formingthe buried metal diffusion layer comprises forming a metal silicidelayer on the surface of the at least one active-device region.
 18. Themethod of claim 17, wherein forming the buried metal diffusion layerincludes selectively depositing the metal silicide layer.
 19. The methodof claim 17, wherein forming the buried metal diffusion layer includesdepositing a metal or metal nitride and annealing the metal or metalnitride layer to the at least one active-device region.
 20. The methodof claim 15, wherein forming metal nitride comprises depositing metalnitride on the buried metal diffusion layer.
 21. The method of claim 20,wherein depositing metal nitride comprises selectively depositing metalnitride.
 22. The method of claim 21, further comprising: selectivelyremoving metal nitride from surfaces of the at least one trench and overthe at least one stacked capacitor structure.
 23. The method of claim15, wherein concurrently introducing comprises concurrently introducingconductive material comprising aluminum.
 24. The method of claim 15,wherein forming the at least one bit line comprises patterning theconductive material located over at least the at least one stackedcapacitor structure.
 25. The method of claim 15, wherein forming the bitline comprising selectively removing the material from locations overthe at least one stacked capacitor structure.
 26. The method of claim25, wherein selectively removing includes planarizing the conductivematerial.
 27. The method of claim 25, wherein selectively removingincludes etching the conductive material.